26 Jan
2011
26 Jan
'11
5:35 p.m.
On 27/01/11 00:38, Keith M wrote:
Nice. You should be able to get a full LatticeMico32 core in there
without any trouble. Bolt on CONMAX, a 16550 and a Verilog ROM and you
can have your own SoC processor :)
That's basically what WISHBONE is --
- DQ is the data bus
- A is the address bus
- CYC and STB start the transfer. CYC is the bus clock, STB is the
bus enable (strobe).
- R/W tells you whether it's a read (slave -> master) or write
(master -> slave) transaction
- ERR tells the master there was a bus error (generally speaking this
would be generated by a memory mapper or MMU)
- ACK tells the master that the transaction completed successfully
Fairly simple. The timing diagrams in the WISHBONE spec make it very
easy to understand.
--
Phil.
classiccmp at philpem.me.uk
http://www.philpem.me.uk/
You're
using an Altera/Terasic DE1 (Cyclone II Starter Kit) developer
board, aren't you?
Close! A DE0. It has a much more capable, but smaller Cyclone III. (15k
vs 18k LEs on DE1) I like the m9k's in Cyclone III instead of m4k's. Sure. I like doing this when I've got a chance of
actually succeeding. :)
Oh aye, there's no fun in a project if it's likely to fail.
If I had unlimited free time then it would be on my
list.
I've yet to find anyone with a decent stock of Round Tuits. Apparently
the Law of Equal Exchange dictates that you can't actually *make* a new
Round Tuit unless you already *have* a Round Tuit...
Did I just reference Fullmetal Alchemist on classiccmp?
Wasn't there something about time and skill being
interchangeable? If
you lack in one, the other makes up for it. Or something like that?
I suspect there are limits to that :)
You could have
an SRAM-like interface, you'd just need to have a BUSY or
DTACK output to go with it. Is that close enough?
Either way, you're not getting rid of the BUSY output...
Yup. That's basically what I imagined. Once the data is "ready",
something is asserted or cleared, and then you read the data.
Definitely what I had in mind.