12 Nov
2005
12 Nov
'05
2:05 p.m.
Subject: Re: FPGA VAX update, now DIY TTL computers
From: woodelf <bfranchuk at jetnet.ab.ca>
Date: Sat, 12 Nov 2005 10:49:26 -0700
To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>
Allison wrote:
So throw away the excess bits. It's still cheaper. Also there is a
Single full adder TTL part the 7480.
Must only be using 7400 and 7404s doing it the
hard way. As far back
as '68 ALU blocks were availble, sure they cost $4 each then but the
chip savings was there.
I was thinking 7401's ( 2 input OC Nands) and 7414's ( hex schmitt
trigger).
Likely you'll never build it.
True, but the chalenge is there. PS if I add as many displays as you say
I need this
will at least look impresive.
Moving up just one step integreation wise
is the 7483 (it equivilent is PDP8 era) full adder. That alone will cut
the ALU chip count.
This is 18 bits ... 2 or 3 or 6 or 9 is needed here, not 2 or 4 or 8
or blah! 16 :) My fun was not
replicating the archetecture in an acient way but using the
most MSI TTL parts I could get to replicate it in a moden way. IE: can I
build a TTL PDP-8 with 1kx4 MOS ram in minimum TTL count for everything
else. One can simplify that to working replica rather than exact replica.
The 8 reduces well for modern chips but the lack of a TTY or a high
speed punch/reader and a
dumb terminal is what is preventing me from build a 8 in 3 CPLD's. The difference
is 2 'ls273 for a 16 bit register or 8 LS74s. But it goes
further with fewer sockets, pins and wires, power and debug time. That
also relects reliability once working as used parts are going to be
a bit shakey untill (re)infant mortaility is again worked out from
removal stresses. That may be minor but with a 200-400 peice TTL system
you would be surprized unpleasently with how bad bring up can be if there
is any uncertanty in the parts used.
I plan to get new parts, but this TTL design will be slower version the
CPLD cpu I am building,
I am going backwards here since other the IDE drive and moden ( 90's )
memory don't want
to have rely on M$ if I want to make a hardware change. ( Ok not quite
true as I'll be using
windows for PCB and CAD work ). When I did the
200 peice TTL system it was 1972 into 73 and we were using
the then common silicone plastic TTL aka the gray plastic and those were
not reliable. That system took over a month to debug between wiring
errors, timing errors (races and spikes) and new but partially dead chips.
and after it was working for about three months after it was cranky when
hot till we weeded out a few more bad actors.
This is making me think twice to goto LS. Now what I need help is with
the J/K flip flops (TTL). 7473 -- "Do not change J/K while the clock is high."
But I want to
STOBE J/K when the clock is high for a D F/F. Will this work in practice? One thing
I'd suggest for those building something greater 50 TTL is lots
of LEDs to indicate the state or status of a block of logic plus the ability
to slow the clock if possible to near DC so you can watch it do stuff
without a fast logic analyser. It's a great fault finding tool.
PS. I got a $5 brick for this years project. :)
Theses days free PC power supplies (usually free
scrap AT form factor)
and cheap brick form factor switchers make 20A at 5 volts a trivial deal.
No wait the brick err door stop is the old PC.