16 Oct
2012
16 Oct
'12
3:22 p.m.
Seth Morabito wrote:
One of the biggest issues with the DEC busses nowadays
is that they use
open collector drivers.
The drivers aren't that difficult. The receivers are more of a
problem. The threshold voltage doesn't match anything commonly available.
Maybe the best bet would be to use a CPLD with open
collector outputs
and +5V tolerant inputs on the other side?
CPLDs (or for that matter FPGAs) don't have anywhere near the output
drive. Also their drivers have edge rates that are way too fast.