24 May
2017
24 May
'17
3:16 p.m.
On 5/24/2017 3:28 PM, Al Kossow via cctalk wrote:
On 5/24/17 12:58 PM, ben via cctalk wrote:
Well I am NOT the world... GOD perhaps.
I know that I make typos and mistakes. More KISS with the design I
am working on all the better. The first version will have NO IRQ's
just to keep the random logic design simple. And just for a change
it will be a 9 bit cpu, with a mini- front panel.
Still fits in 1970's era with logic dropped in price, but memory
still expensive.
Ben.
With typo in VHDL you have hard problem finding
that single gate
error.
The world has been debugging 100,000+ gate systems with simulations for
a few decades now.
Once you've built up a set of test vectors, it actually becomes really
obvious where a single gate error is through simulation.