Motorola EXORset

http://classiccmp.org/pipermail/cctalk/2009-November/278609.html Motorola EXORset Henk Gooijen henk.gooijen at hotmail.com <mailto:cctalk%40classiccmp.org?Subject=Re%3A%20Motorola%20EXORset&In-Reply- To=%3CBAY128-DS3AEB02DB68B6D8DA8B2BB86A50%40phx.gbl%3E> Mon Nov 16 10:04:35 CST 2009 * Previous message: Motorola <http://classiccmp.org/pipermail/cctalk/2009-November/278599.html> EXORset * Next message: IC <http://classiccmp.org/pipermail/cctalk/2009-November/278600.html> DEC8881 * Messages sorted by: [ <http://classiccmp.org/pipermail/cctalk/2009-November/date.html#278609> date ] [ <http://classiccmp.org/pipermail/cctalk/2009-November/thread.html#278609> thread ] [ <http://classiccmp.org/pipermail/cctalk/2009-November/subject.html#278609> subject ] [ <http://classiccmp.org/pipermail/cctalk/2009-November/author.html#278609> author ] _____ From: "Andrew Lynch" <lynchaj at yahoo.com <http://www.classiccmp.org/mailman/listinfo/cctalk> > Sent: Sunday, November 15, 2009 10:40 PM To: <cctalk at classiccmp.org <http://www.classiccmp.org/mailman/listinfo/cctalk> > Subject: Motorola EXORset It is fairly straight forward, as with all 68xx chips. The databus goes to ... the databus. The E clock input connects to the E (sometimes called phi2) of the 6809. The RSx pins go to address lines, depending on your decoding scheme. The normal method is RS0 to A0, RS1 to A1 and RS2 to A2. R/W* goes directly to the R/W* pin of the CPU. CS0* and CS1 go to address decode logic. The chip is selected when CS0* = "0" and CS1 = "1". If you want to use interrupts you must tie the IRQ output of the PTM to the IRQ input of the CPU. As several peripheral devices can be connected to the IRQ pin of the CPU, they are all open collector. So somewhere the IRQ line must have a pull-up resistor. - Henk. ----- REPLY FOLLOWS ----- Hi Henk! Thanks for the help! What I am trying to do is build an IO mezzanine board for the N8VEM 6809 host processor board. I currently have a 6809 host processor board with a 6809 CPU, RAM, ROM, and a 6821 PIA to 8255 PPI "bus bridge" to the ECB. The device appears on the ECB as a peripheral to the Z80 "bus controller". What I am building is an IO mezzanine board for the 6809 host processor which will plug in on top of the 6809 host processor and provide some IO devices. Currently, it supports the 6551 ACIA (working), 6840 PTM (working), and a pair of 6522 VIAs (not installed yet). The ACIA is working since I can communicate with the 6809 host processor and IO mezzanine board using my crude monitor (minibug). I've written a small program to make the output of timer #3 make a square wave so I am pretty sure the PTM is working as well. My major goal of the IO mezzanine board project is to be able to run the Motorola ASSIST09 debug monitor to include the hardware single step mode. The PTM is interfaced to the CPU in the usual way however, the output of timer #1 is also connected to the /NMI line of the CPU. I am since the CPU /NMI is active low and the output of PTM timer #1 is active high (I think), I am running the signal through an inverter. That's why I am asking about the Motorola EXORset because I believe the ASSIST09 was released to support that hardware and I would like to check my design with it. If you or anyone else has any information on the hardware ASSIST09 was originally written to run on please let me know. Thanks in advance and have a nice day! Andrew Lynch PS, I just got the ACIA code (sort of) working in the ASSIST09 monitor. There is still some sort of bug as the input handling is rather screwy but I can get some things to work.