Verilog isn't too hard if you already know C. VHDL is Pure Evil (tm)...
Not in my book that is....
Verilog is severly lacking in basic areas : in my mixed mode (analog /
digital ) simulations I use "std_logic" for digital signals and "real"
for analog signals, bias currents, ref. voltages etc. We also use
different types for the different voltages domains in a chip.
In VHDL this makes an excellent combination.
Verilog just cannot handle this at all. It is suited for simple digital
logic only.
But since, in future, all designs will be done in System-C, only
seasoned C++ progammers will be able to do hardware design....
Jos Dreesen
