31 Oct
2001
31 Oct
'01
5:12 a.m.
At 10:39 AM 10/31/01, Ben wrote:
The VAX series has had PDP-11 front ends that load microcode, run
diagnostics, power cycle the system and boot the operating system. The
D-series of machines from Xerox had microcode that was loaded from floppy,
the IBM 360 machines did an initial microprogram load from floppy, the DEC
10 series had a PDP-11/40 as its console server, there are others. Its a
tried and true technology.
In my case I actually needed the ability to add op-codes and peripherals on
the fly so I don't use PROM. In the mean time I down load new EEPROM
configs on the fly and reset and go, easy to debug and can be shipped as
final hardware as well.
Take a page
from Classic computers as I did and put a dedicated "console
processor" on the front of your FPGA.
Classic Computers??? From where? I am still grumbling that I could not get
front panel interface on my fpga.
This question doesn't make sense, if you want a front panel design it in,
if you're talking about actually manipulating the bits in the FPGA then use
another FPGA to make a JTAG front panel.
I refuse to have a CPU to boot my CPU.
(Note hidden cpu's in HD's count too.) I want to hit reset and have the
CPU load from bootstrap device regardless of main memory. This is the
way I
have the FPGA set up, boot strap from the serial port.
Perhaps we're quibbling semantics. The role of the PIC in my design is as a
serial port, and it has the ability to program serial EEPROMs so I don't
need a special cable to reload the FPGA data, I just power cycle with a
jumper set.
In fact if I had a
PROM bootstrap I would have not worked with my system as wire was broke
in the
middle between the FPGA and memory, and took forever to debug as a data
bit would float.
I guess you lost me here. You're saying that the FPGA configuration PROM
was disconnected from the FPGA and that was hard to debug and so having an
8 pin PIC chip on board to run diagnostics for you in this sort of case is
worthless and antithetical to your design goals?
I've got a
board for doing a "soft"
robot CPU that I hope to get to after BattleBots that has a PIC chip (small
single chip MCU) as the console processor. It loads the main CPU from
either serial EEPROM or from a serial line into the FPGA on power up,
sequences the power, and provides the diagnostic interface when things go
strangely.
Why use a eprom and counter when you can use 50 million transistors.:)
Only after the fpga works 100% will I burn a prom, as the PC --> FPGA is
good way to test the system. BTW the prom for the FPGA is 512k bits or 64KB. I have
a whopping 32K of
memory and will use 8k for a OS leaving 24k for programs. Some how a
FPGA config prom bigger than my basic system hints how big is normal
for everything.
How is this any different than a PDP-11 where the microcode store might
have more bits than main memory? Its one 8 pin part to hold the
configuration information and one 8 pin part to control it.
--Chuck