PDP-8 /e/f/m memory

Ethan Dicks wrote: I had the same idea back in December of '98. I was just looking over my notes, which are not as clear as they should be, but I'll give a try at converting them to a schematic. Here is a summary though: Two 62256 low power SRAMs with 4 bits ignored. The MA bus is buffered and inverted with 74HCT14s. The MD bus transceiver consists of more 74HCT14s, 74LS240 tri-state buffers and 74LS01s OC drivers, all wired together as sort of a DEC005. In retrospect, the 74LS01s are probably a bit weak for this purpose and the 74HCT14s might not have the ideal threshold. The control logic is trivial. The SRAM /CS is effectively grounded. /OE is controlled by MD DIR L. /WE is INHIBIT H NANDed with /OE. Note that just like core, the memory is written after every read. I complicated things a bit because I wanted to have the 3 core fields installed and have the rest semiconductor memory so there are switches that de-assert /CS when accessing fields 0, 1, or 2. I also have a write protect for field 7 so there is a switch that prevents asserting /WE when accessing field 7. I used this for storing a boot loader. The battery backup circuit is bit complicated with lots of 1N914 diodes. I was worried about standby leakage. I even used a reed relay to interrupt /CS on loss of POWER OK H. It seems to have worked though because I am still using the same 3.6V lithium battery after almost 9 years. -chuck