On Jan 24, 2014, at 1:56 AM, Chuck Guzis <cclist at sydex.com> wrote:
On 01/23/2014 09:47 PM, Mouse wrote:
I don't know enough about most UARTs to
comment on them in this regard,
but I think I once saw documentation on one which implied that it was
willing to tolerate receiving a character that was only (what the
receiver's clock says is) only a little over 9.5 bit times long,
because it samples in the middle of (its idea of) each bit time,
starting half a bit time from the beginning of the start bit, and,
provided the stop-bit's sample shows the correct level, it is
immediately ready to accept a new start bit's beginning after that
sample.
But is there any point to that in modern gear? In fact, why not a PLL to synchronize the
receiving clock? Return to mark level by the center of the bit cell should be more than
adequate for most applications.
That's great (and frequently done) if there are enough transitions at
the start to get some sort of PLL lock, but that is typically not the
case with asynchronous comms... you get the start bit, and then you
have data (which could be all zeros). Synchronous protocols like SDLC
have the flag bytes before the transmission, which forms an effective
preamble; most implementations I've seen (granted, not many) often
send two or three flags before the data just to make sure the PLLs
have time to lock before the data starts. SDLC also has fun things
like zero stuffing to ensure that there are enough transitions in
the data to keep the PLL on target.
- Dave