Hi guys,
Is there a defined standard as to when the READY output on a
Shugart-type disc drive should go active?
Not that I a maware of. Are there any standards for anything on that
interface :-)
I'm (slowly!) working through the rebuild of one of the Amstrad drives
(an EME231 I know to have working mechanical components, potentially
good heads, and a fried control board), and I'm stuck on deciding how to
deal with the READY output.
My initial thought was to hold it inactive until a few INDEX pulses have
passed, and the motor speed was within 5% of 'ideal' speed. The plan was
to use a 32kHz oscillator and a 4040 counter to get a several-Hz signal,
then rig up some logic to check that the disc speed was OK, and after a
few valid index cycles enable the drive.
Then I started wondering... am I over-engineering this? Would waiting
for a couple of full disc rotations be enough to reliably generate a
READY signal?
I think that's massively over-engineered :-). Most drives just waited for
a couple of index pulses after motor-on which was enough time for the
thing to get up to speed.
Irony is that the read-amp will probably be the easiest part of the
whole system... I've got a Motorola appnote which basically says "if
you're using a data rate of X and a rotation speed of Y, these
parameters will work" -- X and Y being the two parameters the Amstrad
That is nto too suprising. Amstrad may have done a lot of odd things, but
these drives did turn at 300 rpm and use the standard data rate.
drive uses... That just leaves the write amp and erase
logic to design
(and maybe a 'write lockout' jumper).
I asusme you've looked at some old drive schematics. The write circuit is
normally pretty simple, a divide-by-2 D-type clocked from the WD signal
and reset by WG (to get a consistent starring phase when writing), a
couple of traisnstors to drive the heads and a current sink. And a bit of
enable logic. Often the transistors were part of a tranistor array chip.
Many older 5.25" drives (and 8" ones) didn't use a microcontroller at
all. it was all SSI/MSI chips. So it's fairly easy to work out what's
going on.
-tony