23 Jul
2016
23 Jul
'16
4:56 p.m.
On 2016-Jul-23, at 12:16 PM, Mattis Lind wrote:
So after replacing a microcode PROM on the PDP-11/05
control board and then
concluding that the remaining problem relating to indexed addressing was
caused by one single micro code line that got missing when typed in,
desoldering the PROM, program two more bits (0xf to 0x5), the CPU is now
working. Passing the D0OA diagnostics and the D0NB (except for the mov r0,
(r0)+ tests)
But during the journey the core memory died. I am used to things failing in
my face. The M9301 board started of working. Then it developed some kind of
amnesia, permanently forgetting what was once stored. When this was cured
with yet another PROM, one, then a second DEC8881 driver on the M9301-YF
gave up. But now it seems to work.
So finally I am back to the core memory. Luckily I had a spare set so I
could find at least what board that was failing. Card swapping gave that
the G231 module was at fault. The failure mode is that it does read out the
contents once. The second time it reads out all zeros. Write never works.
Apparently it is the write / write back mechanism that is failing
completely in the G231 module. Since it is in fact reading, the X / Y
selection seems to work and most of the writing takes place on the G110 as
far as I understand since it contains the Inhibit drivers. So what part of
the G231 is specific for the write?
I have a few other G110 / G231 modules with different types of failure
modes so it would be really nice if someone with MM11-L know-how would step
forward and share all the details on this board set.
I will continue to browse the schematic and the user manual to try to find
the failing component, but help is highly appreciated!
Speaking generally, without specific familiarity with these dec modules . .
Writing is performed by driving the X/Y lines in the opposite polarity (current direction)
than for reading.
Have you checked whether it affects the entire memory module or some block or selection of
addresses within the module?
If it's a limited set of addresses it may just be an X/Y driver transistor for the
polarity appropriate to writing.
If it's the entire module, you might look at how the drive polarity selection is done
for the X/Y drivers,
somewhere it should trace back to the R/W/restore state sequencing for a memory cycle.
The problem may then be in that polarity selection or the state sequencing.
The inhibit circuitry does just that: inhibits writing (inhibits setting the cores to the
'set' or 'written' state),
so it doesn't sound as much like an inhibit issue, unless it's something like the
inhibits always being enabled.