25 Oct
1999
25 Oct
'99
4:54 p.m.
Tony Duell wrote:
All of the Intel ap notes I've read recommend either active-low level
sensitive, or falling-edge sensitive. Sure, you can set the bits to the
other two modes, but nowhere does Intel suggest that it's a good idea.
I don't recall an Intel app note showing the DMA
'extension' registers,
to get the 8237 to work with the 8088. Most likely Intel would have been
pushing the 8089 (even though it wasn't out in time...)
Too expensive. IBM couldn't put expensive chips in it, even if they
were available. So they did a quick hack to add the register. Maybe
that detail isn't direct from an Intel ap note, but it's not exactly
rocket science either.
The RAM timing, etc looks decidedly non-intel as well.
Intel had RAM
controller chips IIRC. IBM used TTL and a delay line.
Intel had a cheap DRAM controller that wasn't good enough, and a good
enough one that wasn't cheap. DRAM controllers using TTL and delay lines
were certainly common enough elsewhere. Again, this isn't really a
sign of any ingenuity on IBM's part.
Maybe every detail of the schematic wasn't pulled from Intel ap notes,
but a pertty significant portion was.
The peripheral cards are not Intel at all.
Nor did anyone claim they were.
If the IBM engineers had designed more of the cards earlier on, they
wouldn't have put such a crappy bus design, particularly with regard
to the interrupt control.
1) The way
that the 8259 interrupt controller is used: IBM botch this
severely.
Hmm... Well, the active high edge triggering doesn't help ;-). But that's
an Intel documented mode for the chip. In what other ways did IBM botch
this. IMHO the 8259 is used almost as Intel would have done.