OT: DRAM memory controllers within FPGAs

On 26/01/11 18:19, Keith M wrote: If you mean single-data-rate PC100 SDRAM, then yes. I used to use an OSS/FS IP core until I found out it wouldn't work on the Xilinx platform. It synthesized, but the resulting microcode wouldn't actually work... Ended up rewriting the stupid thing... I started from the ground up, eliminated the concept of caching reads/writes (I wanted this for a CPU core which already had an Icache and Dcache built in), and went for the "simplest option". Took me about three days to get it working and properly parameterise the Verilog code. You can change (at build time): Data bus width (link to CPU) Number of SDRAM column address bits Number of SDRAM row address bits Number of SDRAM bank address bits CAS latency T_rp, T_rcd, T_rfc, refresh rate, initialisation delay and time before enabling CKE None of these are adjustable at runtime; that's been on my TODO list for about six months. Ideally I want to add a control bus to it, which will allow the host to change the SDRAM timings as required. I'll probably need this if I ever want to tie it to a PC SDRAM DIMM. The hardest part is getting the timing right. Screw up the refresh timing and your data will mysteriously corrupt itself over time. Screw up T_rp, T_rcd or T_rfc and you'll have issues with missed reads and writes. Screw up the initialisation and the chip just plain won't work right. And yes, my version works on both the Xilinx and Altera platforms :) The solution for that is parameterisation. That's always fun. If it isn't WISHBONE or something similar, then I won't touch it with a barge pole. Building a WISHBONE-to-AVALON bus bridge is a pain, too -- I never managed to get mine to work. No comment. The 16550 UART and WISHBONE CONMAX cores are pretty nice once you figure out the interface. The bit-width adapters are buggy (as in, "don't work at all") and I ended up rewriting them for my use. The LatticeMico32 core falls into this category, but I've forked it and started maintaining a "vendor independent" patch set. Still haven't got JTAG Debugging working, but that's probably more a case of "throw some time at it" than anything else. You can't really adapt SDRAM to an SRAM type interface because of the way SDRAM is addressed. If you're already in the right bank and row, then you're more or less fine. If not, then you have to do a bank select and row precharge. That takes a couple of clock cycles to kick in, so you need to tell the host to wait a little while before reading the data bus. With CPUs like the Motorola 68000 series, you just hold nDTACK high for a little while. With the 6502 you have to stop the clock... though why would you attach an 8MB or so SDRAM chip to a 6502, anyway? -- Phil. classiccmp at philpem.me.uk http://www.philpem.me.uk/