On 2012 Mar 15, at 9:22 AM, Gergely L?rincz wrote:
*Could you be having a problem with your RUN/LOAD
switches so that the
processor is _not_ in LOAD state when you think it is?*
Actually, I checked them millions of time by probing the WAIT and
CLEAR
(pins 2&3 of 1802). In load mode, both of them are low, in run mode
they're
high and TPA%TPB send timing pulses. Also, the SC0 pin goes high/
low as you
flip the load and run switches. I cannot think of any other means of
testing the run and load switches but they seem to work and the 1802
behaves accordingly. However, the 4013 still doesn't work properly.
I have
trouble understanding how it works. It seems to me that when the input
button is pressed (or released), the Q_ should send a pulse to DMA
IN then
the SC1 should change its state (since DMA IN's state changed) and
send a
short pulse back to 4013. In other words, once the Q- output sends
a pulse
to DMA IN and SC1 sends a pulse in return, which resets the
flipflop. Am I
right? At the moment SC1 doesn't do a damn thing (since DMA IN
doesn't get
a pulse). Any ideas? I'm beginning to grow a beard, chain smoke and
eat
cold leftover from the fridge. Wife's worried and complains. Any
help would
be appreciated!
Yes, that's the idea:
- The release of the INPUT switch results in a +edge on the 4013
clock (11)
- The +edge sends the nQ output (12) low and hence nDMAIN low
- the 1802 enters DMA state, sending SC1 high
- SC1 high resets the 4013 through the diode OR gate, sending nQ &
nDMAIN back high
- the 1802 exits DMA state, sending SC1 back low, completing the DMA/
load/examine cycle
nQ & nDMAIN will only be low for a microsec or two, SC1 will only be
high for a microsec or two.
Debugging trial: remove the connection from SC1 to the diode at the
4013 reset (10).
Now, when the input switch is released, nQ & nDMAIN should go low and
STAY low as there is nothing to reset the 4013 (until you flip the
load mode switch).
It follows SC1 should go high and stay high or repeatedly pulse high
as the 1802 is being held in the DMA state (which I think you already
tested by forcing nDMAIN low).