24 Oct
2018
24 Oct
'18
7:05 a.m.
On 10/24/2018 09:19 AM, Paul Koning via cctalk wrote:
I found that paper to be a not so interesting and more or less
pointless.? For many applications its what's on the
chip and rarely does it focus on architecture.? Engineers need to do
things or produce things that work
and? most of the time it comes down to whats available and price.? With
embedded machines the IO
capability and resident memory are likely deciding factors more so than
if its Harvard or Von, RISC
or CISC.?? The other is the tool chain costs in, acquisition cost,? time
to learn, and apply.
Allison
On Oct 23, 2018, at 7:08 PM, Noel Chiappa via
cctalk <cctalk at classiccmp.org> wrote:
...
There was a recent discussion about code density (I forget whether here, or
on TUHS), and someone mentioned this paper:
http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf
which shows that for a combo of benchmarks, the PDP-11 had the densest code
out of all the ones they looked at. (They didn't look at the PDP-8, but I
suspect that since it's a single-address design, it's almost ceertainly not
as dense.)
The PDP-11 dates back to the days of core (it went through several generations
before DRAM arrived - e.g. the -11/70 originally shipped with core), and given
core prices, minimizing code size was pretty important - hence the results
above.
What's interesting is that the paper uses compiled code. The gcc back
end for pdp11 is still a work in progress and clearly doesn't deliver best possible
code, certainly not back then.
paul