Hi,
I think I have arrived at pretty much the same point as Jay on my 11/45. =
Ive stripped it down to the minimum - processor, memory management, =
memory (UFUM) and timing generator.
Toggling in from the front panel, I can see the data lines change, but =
I'm not getting address data on the Unibus.
My next test, is to try and look at the address data between the =
processor and the memory management module.
Does anyone have any other tips?
A general comment : If you're missing an entire data or address bus, it's
more likely you're missing an enable signal than all 16 or 18 drivers for
whatever set of lines have failed at once. So I'd do essentially what
you're doing (trace the lines backwards towards the source), then start
looking at enables for whatever stage seems to have failed.
-tony