6 Jan
2002
6 Jan
'02
2:51 p.m.
Richard Erlacher wrote:
Another option would be to try to fit the
schematic-based design of the
original controller into a CPLD. (NOT and FPGA!!!) I've found that
schematics of "old" logic seem to yield useable circuits in CPLD's, while
FPGA's totally seem to want to ruin the timing. That would lead to a circuit
about the size of half a dollar, that's easily modifiable, since the parts are
in-circuit-reprogrammable.
I never really trusted FPGA timing. I expect that unless you have
oneshots or glitch sets and clears timing should be simple.
None the less you do need to know what your logic does!
I think a digital data separator is just a counter that clocks
a shift register, with timing reset by the data stream.
Busy cooking supper so I can't look up more info.
--
Ben Frantic - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html