IWM refers to the "Integrated Woz Machine" if I remember correctly (I'm an
Atari Historian, not an Apple Historian)   Tom Owad could probably answer
more correctly.    Apple did a wonderful job at making a system not only
flexible and efficient for disk drive access for a personal computer, but
made it cheap, really unlocking the ability for the average user to finally
have a decent storage medium that was fast and reliable.
Curt
----- Original Message -----
From: "Sean Gugler" <gugler(a)agames.com>
To: <classiccmp(a)classiccmp.org>
Sent: Wednesday, September 05, 2001 6:36 PM
Subject: Re: Apple ][ disk controller state machine
  Thanks, dq.  I have seen that doc, but it speaks
mainly of the
 3.5 drive, which had several enhancements not available on the
 5.25 drive.  Was the Apple ][ controller sufficiently similar to
 the IIgs and progeny that this documentation is appropriate for
 it also?  I've never heard the Apple ][ controller chip referred
 to as 'IWM' -- is that my ignorance, or was the chip renamed, or
 are they (maybe slightly) different beasts?
           - Sean
 Douglas Quebbeman wrote:
 >
 > > Until I get my hands on a copy of the venerable "Beneath Apple Dos"
 > > is there anyone who can point me to an online resource describing the
 > > Apple ][ disk controller P6 ROM state machine?  The exact uses
 > > for the Q6 and Q7 switches ($C0EC-$C0EF)?  Or would be willing to
 > > summarize from the mighty tome for me?
 >
 > From:
 >         
http://www.mac.linux-m68k.org/devel/iwm.php
 >
 > : =======================
 > : Accessing IWM Registers
 > : =======================
 > : The IWM chip has several internal registers available to programs.
 > : Access to these registers is controlled by the Q6 and Q7 switches.
 > :
 > :       +=====+=====+=======================================+
 > :       | Q6  | Q7  | Register                              |
 > :       +=====+=====+=======================================+
 > :       | off | off | Read data register                    |
 > :       +-----+-----+---------------------------------------+
 > :       | off | on  | Read handshake register               |
 > :       +-----+-----+---------------------------------------+
 > :       | on  | off | Read status register                  |
 > :       +-----+-----+---------------------------------------+
 > :       | on  | on  | Write mode register (if drive is off) |
 > :       |     |     | data register       (if drive is on)  |
 > :       +-----+-----+---------------------------------------+
 > :
 > : The mode register is a write-only register containing several flag 
bits
  > : which control various features if the IWM.  To
access it, turn off the
 > : drive (by accessing ENABLE), turn on Q6 and Q7, and write to any
 > : odd-numbered address in the $C0E0...$C0EF range.
 >
 > hth,
 > -dq