18 Nov
2010
18 Nov
'10
11:21 a.m.
SRAM's almost always have the concepts of
"row" and "column" select
internally but rarely is it obvious from the outside.
As does core memoroy (of course), core-on-a-rope ROM, that HP inductive
ROM in the 9100, many other ROMs/PROMs/EPROMs, and so on. It simplifies
the address decoders.
Sometimes the data sheets for an SARM (or whatever) indicate the
row/column structure. Not that it matters, I've not come across an SRAM
that has, say, faster access time from a change in row address than a
change in column address
-tony