5 Aug
2011
5 Aug
'11
8:27 a.m.
On Aug 5, 2011, at 8:15 AM, Jochen Kunz wrote:
On Thu, 4 Aug 2011 19:37:35 +0100 (BST)
ard at p850ug1.demon.co.uk (Tony Duell) wrote:
You also might want to look at: http://www.shiresoft.com/products/ua11/Unibus
Analyzer.html
(and yes, it's a shameless plug!).
TTFN - Guy
Eh? The SPC signasl are a rearrangement of the
Unibus signals
I know.
The HALT signal is not, AFAIK, a Unibus signal at
all.
And this is the problem. These signals are available in a SPC slot and
used by the console but not covered by the Unibus documentation. I
still have to google for a description of those signals.
Incidentalluy lookign at Unius cycles with a
logic analyser is quite
easy. I normally trigger on the falling edge of MSYN, qalified by the
address lines. You need a lot og LA channels to be useful, though.
I have 40
channels at 50 MHz or 16 at 300 MHz. That should be enough
for some basic testing. A friend gave me an isolating transformer. So I
can exclude ground loop problems. He will give me a logic probe also
next week. This seems to be a simple but helpfull and effective test
tool.