It occurred to me that maybe I'm trying to shoot a duck with a howitzer.
A 16-bit ISA implementation with FIFO should have enough moxie to sustain
the data rate I'm looking at using DMA transfers. Normally, this would
limit one to 128K transfers, but the 8237 DMAC has the auto-initialize
function, so I should be able to pull data out of the DMA buffer fast
enough to handle any length record. Circular buffering of a sort. A 512
word FIFO would allow for almost a millisecond of latency, so even if I had
to do without autoinitialize, I should be able to, even under Windoze
(perish the thought!).
This would simplify design and implementation tremendously.
Whatcha think?
Cheers,
Chuck