Dave McGuire wrote:
The whole
point is FPGA/CPLD/PAL design is available for the average
working person. Large scale chip design is *not* to my knowledge[1].
But FPGA/CPLD/PAL design *is*...and why wouldn't you want to use
professional tools instead of toys? Real tools are available.
PS. I have a design concept with about the same
number of gates as
6809 or a Z80.
Cool! Describe?
See: CPLD design. This current design is CPLD/2901 bitslice design.
The ALU is 12 bits, double clocked to give a 24 bit CPU on a 6800/6502
style memory cycle.One CPLD is for high speed decoding and the other
for the MAR and MBR data paths. A 8 bit refresh counter is for DRAM's. A
2.5 MHZ (top speed)clock gives a 800 ns memory cycle. 3 2901's make
up the data path.
A LSI version would have 24 bits in the ALU, but with a 3 bit carry
skip adder. The logic design is slow but simple, with decoding taking
the first clock cycle and the second cycle for alu operations.
-Dave
Ben.