8 Jan
2017
8 Jan
'17
10:11 a.m.
On 08/01/2017 17:21, "Tony Duell" <ard.p850ug1 at gmail.com> wrote:
The whole unit is monochrome, it only has a little 5" B&W TV as its output
device -
http://www.binarydinosaurs.co.uk/STCExecutel01.jpg
However, two of us bought units at the same time and the other one has a
little bridgeboard containing a 74LS244 that sends the RGB signals to a DIN
socket on the back of the case for an external monitor. I also can't see a
luminance line on the connection to the TV board on mine, just
red-green-blue with sync and inverse sync which go to the horizontal driver
chip and vertical driver chip respectively. You may remember I was asking
questions about these chips a couple of months ago because that TV board
suffered some component rot and I thought the wavy picture was because of
that.
Clutching at straws :)
I photographed
both sides of the board and merged the pictures together to
make a front/back composite. The trace for the cathodes of the 3 diodes
links together on the back of the board and doesn't go anywhere else. The
front trace from V302 cathode goes straight to R312. The anodes DO link with
the monitor driver board through the connection marked MON though.
OK, probably some kind of luminance signal. Was there ever a monochrome
version of this unit? 
One of the
reasons I'm asking these questions is I'm trying to see if
there's another source of composite sync given that the MR9735 itself
doesn't do it, even though it should.
I doubt it.... Why would there be? Is the MR9735 doing anything? Is it accessing memory,
for example?
I still wonder if it has to be initialised (say to vewdata rather than
teletext mode) and if this is not occuring.
Its address and data buses are active as is the pair of 2114s that are
acting as a page store. There's a 74LS240 buffering the data bus and that's
active.
You could be right though, I'm not convinced the unit is actually running
any code yet despite the ROMCS lines working and I can see activity in all
16 RAM chips. Data bus and address bus at CPU and ROM chips looks happy from
a 'doing something' point of view. All the control lines on the CPU are
pulsing with the exception of IO/M but if all the IO the chip is doing is to
memory then that's to be expected.
I've disassembled the ROM code so I'll have a look through that for an init
routine, also the datasheet should tell me what its expecting at powerup.
Cheers,
--
Adrian/Witchy
Binary Dinosaurs creator/curator
Www.binarydinosaurs.co.uk - the UK's biggest private home computer
collection?