24 Aug
2005
24 Aug
'05
2:11 p.m.
From: "Allison" <ajp166 at
bellatlantic.net>
---snip---
ugly 8080 flavor for transfers up to 1KB:
; HL is memory pointer
; A is temp
; B is transfer length *4
; Zero flag affected by DCR B
DMAIO: IN DMAport ; wait if DMA is not asserted
mov M,A
INX H ; HL<-HL+1
IN DMAport ; wait if DMA is not asserted
mov M,A
INX H ; HL<-HL+1
IN DMAport ; wait if DMA is not asserted
mov M,A
INX H ; HL<-HL+1
IN DMAport ; wait if DMA is not asserted
mov M,A
INX H ; HL<-HL+1
DCR B ; B is dmatransfer down counter
JNZ DMAIO ; loop if not Zero, more to go.
...
Hi
As I recall, you could move the DCR B before the last
IN DMAport. As I recall, INX H didn't effect the zero
flag ( or was that the carry flag ? ). In any case,
This kept the last time shorter.
Dwight
It's 35 cycles in z80 for the slowest part of the
loop
and 34 for 8080. Z80 IN port is 11cy!
Why four bytes pwer transfer? one it makes doing 512 or
1024 bytes per sector with a 8bit counter (lower overhead)
and doing a 765 format only requires 4 bytes per sector
(C, H, R and N)!
A 2mhz 8080 will actually run this for 8" DD (13us case)
successfuly even though the last leg of the loop is
17.5us as you have 16us +13us worst case before an
overrun occurs and the next step in the loop is not
as slow. Note waits for refresh will blow the works
and Z80s systems that use processor refresh are not
likely to behave well if the FDC hangs (no disk or
blank inserted) too long.
A 6502 can easily do it.
From a system perspective I prefer DMA. I like to
free
up CPU cycles to do "stuff" and make hardware do repeatitive
stuff like basic transfers. However the DMA does not have \
to be complex or even a LSI (8257 or 8237). A simple gating
logic plus an upcounter of sufficient length is enough and
it can even be to a fixed address (host buffer in the case
of CP/M deblocking). Things like background tasks are then
easier to implement to utilize otherwise wasted IO loops
(wait for keyboard!). The most obvious interrupt driven
background tasks to implement are printer output buffering
or modem input buffering.
Allison