17 Feb
2015
17 Feb
'15
12:35 p.m.
So the description of the SSR3 register in "Microcomputers and Memories"
(1982), on pg. 284, apparently has an error. It describes bit 5 as "enables
I/O mapping", but.... the QBUS 11's don't have any kind of I/O mapping that
I
know of. Or am I confused?
Noel