QBUS/UNIBUS transceivers (again)

Hey all, Since I'm stuck in a hotel for the IEEE LCN conference, I had nothing better to do than look up lots and lots of datasheets in search for an ideal driver/receiver pair for modern DEC bus circuits. Warning: below is a lengthy missive. Ignore it if the subject line doesn't turn you on (so to speak). The driver is generally the easy part; there are quite a few FETs out there that ought to do the job acceptably. You need a total (driver + receiver) capacitance of 9.35 pf, which is generally the tallest order, but it's easy enough to limit the slew rate of the pulldown by putting a series resistor in line with the gate. I believe Peter Wallace recommended the FDV301N, which seems as good as any; put one for the driver and one at the source as a gate for a group of them, and you should have a pretty effective transceiver. It might take a bit of space, and you'll eat a lot in assembly if you're not doing it yourself, but as Dave McGuire pointed out, if your main logic is contained in a micro and/or CPLD/FPGA, you're going to have plenty of space. And for SOT-23 packages, you can probably get close enough to the density of the original (quad-gate) DIP devices. The FDV301N claims a Coss of 6 pf, though I haven't done my homework to think about how the other parasitics affect the input capacitance. The receiver is a little harder. In the National (now re-branded by TI, which is hilarious considering the part was obsolete and long out of production by the time TI acquired them) app note on the DS3662, they indicate that they essentially just did the obvious thing and used a comparator for the input. Doing so with discrete comparators is possible, but generally costly in terms of both money and board space, and I've found parametric searches of comparators to be a bit tricky, depending on where you look. At least looking through what Digi-Key offers (and they're pretty much the best parametric search I know), there are few quad units fast enough which don't break the bank. The MAX9108 is a good candidate, though (quad gate for $4, or $2 in quantity 100, which you'd certainly be looking at for more than one or two units). It's a TSSOP-14 package, which isn't exactly tiny, but it's smaller than a DIP in most respects. It has a dual-element cousin, the MAX9107, which comes in a SOT23-8 package; I believe you could achieve higher density that way, though you'd end up spending more per gate. The input bias current is in the sub-uA range, but there's no input capacitance listed, which bothers me a bit. The outputs are TTL-compatible, which is generally compatible with 3.3v logic as well; it has a typical Voh of slightly more than 3.3v, but at 100uA source current, which is well within the handling range of the built- in protection diodes of most FPGAs (and it's close enough that it probably wouldn't trip them). Another good candidate is the NE521, which has some very nice logical gating inputs (which would save some external components if you're using bidirectional lines on the FPGA side). It's also a dual part, but unfortunately only available as small as SOIC-14, which doesn't provide for a lot of density (it is available in DIP, though, which should make some people happy). Its propagation delay is 12 ns instead of the MAX910x's 25, though both are still comfortably below the 32 required for DEC buses. Bias current is a max of 40 uA over temperature range (DEC max for the receiver unit load is 80 uA). It also does not provide an input capacitance; I suppose it's common with comparators? This one is also not as cheap per gate; even in quantity 100, it's still almost $4 each ($2 per gate), which probably offsets the convenience of having the enables built in to the part for most people (especially considering the larger package size). In any case, the solution doesn't seem as infeasible as I previously thought. Anyone want to go in on a few test boards together to split the costs? It seems like it would be prudent to make a few short (2 inches, maybe) dual-width boards to test input and output capacitance/waveforms before we try making whole boards, and if someone has a UNIBUS machine they're willing (and able) to test out on, that would be handy since I definitely do not. Also, are there major flaws in the above analysis? Am I totally smoking crack? The app note I referenced is here: http://www.ti.com/lit/an/snla139/snla139.pdf There's another interesting related one here: http://www.ti.com/lit/an/snla134/snla134.pdf - Dave