A cute trick commonly used in the CP/M days (and
later) was to put a
boot EPROM board in the same (conflicting) memory space with RAM; the
EPROM code would proceed to "block copy" itself in place (read: EPROM;
write: RAM) then reset a flipflop that enabled the EPROM board.
EPROM board read access generated many wait states; the trick was the
EPROM board ignored write cycles but the underlying RAM didn't. I forget
how we handled the EPROM 'read' cycle but it was buss-safe (S100) and
simple.
I believe that was the "PHANTOM" line... pin 67 (according to _THE_S-100_
AND_OTHER_MICRO_BUSES_ by Poe and Goodwin).