On 5/30/2010 8:15 PM, Ethan Dicks wrote:
Were there any versions of the 6522 (65C22?) that had the shift
register bug fixed? Does the 6526 preserve the bug? With all the
The 6526 fixed the bug, though it has a bug (bugs) of its own.
Jim Butterfield noted in a post long ago that the hardware guys knew
about the 6522 shift register bug long before the VIC-20 was in
development, but due to "right hand, left hand" stuff, that information
never got communicated.
The story continues that when the C64 was in development, the switch to
the 6526 would allow a return to the shift register usage. The
designers added the requisite lines to the PCB design, but during the
cost reductions/final design work done in Japan, the extra lines were
removed. When the PCBs came back from the initial run, the PCB designer
in the US was apalled to find his extra lines had been removed.
So, for that
bug, the serial speed went from CLK/32 to
transfer a byte down to CLK/320 or so.
I hadn't realized it was that much slower. Wow.
Well, I'm sure anal pedantic folks might quibble over the values, but
here was my calculations:
6522/6526 shift register operates at CLK/4 top speed. So, 8 bits take ~
CLK/32
On the VIC-20, the CLK is 20uS per half cycle. That CLK/40 per bit, or
CLK/320 for the byte.
Both calculations ignore TURN and other protocol nuances.
The C64, due to the DMA needs, reduced the 1541-C64 speed to CLK/60 per
half clock cycle. So, a byte takes CLK/960, or ~ 1000 bytes/sec. In
reality, my numbers are off, since most references acknowledge a top
speed of 300 bytes/sec for the 1541, though some of that is probably due
to sector latency and the protocol overhead.
My first C-64 (S/N P00002007, a development machine
sent from
Commodore to my first employer) came with a 1540 and some extra
operational instructions - I think it was to disable VIC-II DMA, like
the KERNEL already does during a tape load.
Yes, disabling the VIC-20 will allow VIC-20 speeds. Some fastloaders
did this to allow ignoring the DMA issues.
Jim