9 Sep
2005
9 Sep
'05
4:40 a.m.
> If the DIN and DOUT are common on the MB
Well, darn it, they aren't linked. It turns out
that the memory
controller on the
IIfx buffers the writes, so that the CPU can go do something else
after only 2
cycles instead of 6, unless, of course, the next operation is a
memory access.
So the the data lines from the SIMMs are routed to
74F573 D-type latches. It
appears that the SIMM's DIN comes from the latches' outputs and DOUT goes
to the latches' inputs.
Okay, what if I put a pair of octal tristate buffers on the SIMM and
control them with the Write Enable line such that data can go from
DIN to the DRAM chips' data pins when WE is active, and data can go
from the chips' data pins to DOUT when WE is
inactive?
Something like the SN74ABT541 looks like it might do the trick:
<http://focus.ti.com/docs/prod/folders/print/sn74abt541b.html>
I see two potential problems. First, the buffer will introduce about
4 ns (max) of delay between WE changing and data flowing, so timing
might be dicey. Second, the timing will be even tighter, if the
computer tries to do a Read Modify Write to memory.
So one important question is whether the IIfx makes use of the Read
Modify Write function of DRAM. Checking some old datasheets, it
appears that that feature was present in old DRAM chips. Did
computers typically make use of it?
The tristate buffers are only about $.50 each, so they don't add much
to the cost, but they might blow the timing.
Jeff Walther