I was curious ... pulled out a bunch of NOS 74x175s
and did some tests. I noticed that the behaviour was
sensitive to Vcc and ended up with the following table.
The values 0<=n<=4 in the matrix indicate the number of
flip-flops in the IC which worked as desired, so 4 is 'good'.
<--> repeat across
--> progression up
<-- progression down
Vcc
Unit MFG DEVICE DATE 4.1 4.3 4.5 4.7 4.9 5.1 5.3
---- --- ------ ---- |---|---|---|---|---|---|---|
1. TI 175 7340 4 4 4 3 3 3 3
2. " 4 <--> 4
3. " 4 4 4 4 3 3 3
4. TI 175 7624 0 <--> 0
5. Hit 175 6G46 4 3 <-- 0
6. TI S175 7340 4 <--> 4
7. " 1 --> 3 4 4
8. " 0 --> 3
9. " 2 3 4 <--> 4
10. TI S175 7936 4 <--> 4
11. " 4 <--> 4
12. " 4 <--> 4
13. " 4 <--> 4
14. NS S175 8742 4 <--> 4
15. NS LS175 8332 0 <--> 0
Observations:
- behaviour may differ between IC units even within valid Vcc range,
- a given IC unit may change its behaviour within or near valid Vcc range,
- 175 class may pass at lower Vcc and fail at higher Vcc,
- S175 class may pass at higher Vcc and fail at lower Vcc.
Interesting the way 175 and S175 devices differ in their response to Vcc change.
The group of TI S175s from 1979 did seem to show reliable behaviour over the
entire range.
One way or the other, the DEC front panel is relying on unspecified behaviour
of the device. I wonder if the designers were just relying on old habits of
setting flip-flops via collector triggerring from the discrete days, and just
got lucky that it worked.
(Another observation was that the clock input *must be held low* for any
of the devices to work as desired.)