18 Dec
2008
18 Dec
'08
11:36 p.m.
From: "Philipp Hachtmann"
Sent: Thursday, December 18, 2008 11:16 PM
The advantage being that you didn't need to round up all the signals
and OR them yourself :-). (I believe you do get yet more warnings,
though.)
Well, that's a matter of perspective, since the end of TS4 is just as
easily thought of as the start of TS1. Thus TP4 triggers the setting
of TS1 and initiates all the work of TS1.
Not sure what the epithet "sequential coding" means in this context.
There is combinatoric logic elsewhere computing the new values for
these 6 latches, which take their new values at the beginning of TP4.
You can
emulate that in std_logic with a single driver driving an "H"
(the "pull-up"), and everyone else drives either "0" or
"Z".
Yes. You can write that. But the synthesis tool - if it eats that -
will
generate
many ORs... So avoid it. In the company I have worked a bit for, MANY
constructs
were simply forbidden. Thinks like Z, H, L in std_logic are suspicious :-) No, I'm
trying to re-express everything in a few clock domains, namely
the timing pulses at the beginning of the cycle. The rest goes in the
combinatorial part of the thing:
Timing pulses come at the END of a timing state!
TS1 is the state, left with TP1... if
(tp4'event and tp4 = '1') then
fetch <= f_set;
defer <= d_set;
execute <= e_set;
word_count <= wc_set;
current_address <= word_count;
break <= b_set;
end if;
That's sequential coding!! I once thought of a gate level transformation of the
Honeywell H316 into
an FPGA. That's even more
difficult: Nearly the whole machine is built from NAND-gates :-)
So they have really cool things like a flip flop with many OC gates
pulling it down. And no clock at all, only transport pulses...
Much of the earlier R/S stuff in the straight-8 feels that way to me.
Lots of transistors just being yanked this way and that. Then again,
every time I look at the 8/i drawings, they seem more synchronous, so
maybe it's just that I haven't fully understood the older machines yet.
Vince