31 Jan
2021
31 Jan
'21
10:03 p.m.
On Jan 31, 2021, at 8:19 PM, Josh Dersch <derschjo
at gmail.com> wrote:
Well, what's interesting here is that on my system, switch S4 (MAINT STPR) steps the
processor with switches S1 and S2 set to *any* configuration.
Hmm, would expect to see S2:1 S1:0 step by microinstruction, and S2:1 S1:1 step by clock
phase. The other two settings should free run the microcode. So yeah, sounds like
something fishy there... The TIG card has more than a few analog components, and its not
too unusual for these to get hung up on the adjacent card and have a leg pulled or sheared
from the board.
Ah, and page II-6-20 (p. 178) indicates that when DCLO
is asserted, it asserts: "UBCE ROM INIT H - forces the ROM to ZAP.00 (200), and stops
and clears the Timing Generator and the Cache timing."
Yup, that's one of the signals coming in to RAC E106. Probing there should indicate
which of possible sources for ZAP is actually occurring (UBCE ROM INIT H on pins 2 and 3
there).
DCLO is a classic... Make sure to 'scope it, because it sometimes has troublesome
spikes that don't show on a multimeter. If you have H742s, there are some wet
tantalums on the control board that sometimes leak and cause trouble with this.
I'm sure you are raring to go -- hope those fans show up for you tomorrow, and will be
interested to hear what you find!
--FritzM.