9 Aug
2008
9 Aug
'08
12:49 p.m.
The 18 pin-per-package limit claims regarding the 4004
and 8008 have
been around for a long time, and I think they came from interviews with
Intel's founders and/or early employees, but I think they're factually
incorrect, at least as commonly stated.
The 24-pin DIP was very well established by 1968, and was already used
by TI at that time. There were certainly higher pin-count packages at
that time also. I'm not sure about the 40-pin DIP, but in 1969
Fairchild was shipping at least one memory chip in a 36-pin DIP, though
that particular package never became popular.
I would find it hard to believe that 24-pin and higher dips were
unavailable.
I have a couple of Sharp calculators from about that date. I just
grabbed the nearest (an ELSI-160) and opened it up, to find that the
four chips have date codes in early 1971 and forty-two (yes, 42) pins
each in a dual zigzag arrangement. The pins are spaced at 0.05 inch,
and alternate pins stick out 0.1 inch further than the rest. The whole
is a gold-top ceramic package a little smaller than a 24-pin DIP.
(FWIW at least one of the calculators has edge connectors with a pin
spacing of 1.25mm. But the chips are still 0.05", i.e. 1.27mm. And
yes, you can tell the difference. For the early '70s, this is high
precision stuff!)
Possibly whatever specific company Intel was
contracting with to supply
lead frames and ceramic packages didn't yet offer higher pin count
packages, but they obviously were available from some vendors since
other semiconductor companies like Fairchild and TI were using them.
That makes sense. I think someone said it already: if the chip was a
custom job for a lowish-volume contract, Intel wouldn't want to go and
find a new packaging contractor for it.
Philip.