14 Aug
2006
14 Aug
'06
9:54 a.m.
vrs wrote:
I looked at doing one of these, but got kind of lost
about how
the timing signals are used. I looked at the MOS RAM for the 8/A,
but there's all this cruft for refresh in there, some stuff about
suppressing access during ROM access, etc. And then it looks like
the memory timing signals are derived somehow from the memory
refresh stuff??
Is there a nice place where the Omnibus memory interface control
signals are explained somewhere?
I did a semiconductor memory design for the OMNIBUS several years ago.
It was for an -8/e and 32kW using two SRAMs. I never got to documenting
it outside of my notebook, but if there is enough interest, I could do
some schematics. It is battery backed, so its pretty much equivalent to
the core I was replacing.
The Small Computer Handbook, the maintenance manuals and timing diagrams
from the processor print sets had enough information
for me.
-chuck