15 May
2002
15 May
'02
5:10 p.m.
"Dwight K. Elvey" wrote:
One of the 4's was for the bus size. It was a multiplexed
synchronous bus. It had 8 phases. 3 were for address and
one was for the rom. One or two were alu and I don't recall
what the other was for but I think it was bank selects.
Each device would watch the instruction and would do the
right thing ( I/O or RAM ) when it's time came around.
One might call it smart I/O. This way, the processor didn't
have to have the additional pins to select the function
for the bus.
Dwight
I read many moons ago that Intel at that time could not package
a chip with more than 16 pins, until the 8080. That was a
nice chip for the time. Notice too how the leading edge of
CPU's have been around $350 US each starting with the early
Intel chips and continuing to today.
--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html