2 Nov
2010
2 Nov
'10
12:19 p.m.
On 2010 Nov 1, at 5:35 PM, Chuck Guzis wrote:
On 1 Nov 2010 at 17:41, Brent Hilpert wrote:
I'll eliminate some of the grunt work for folks and offer the
following document, which contains all of the Karnaugh maps and a
simple logic diagram.
http://www.strivingafterwind.com/EE/EE112/ee112formal.pdf
I'd probably start by using a 7404 and distribute the binary input
and its complement... :)
Starting with those karnaugh maps (there's an error in the schematic),
there is a solution with 10 packages:
1 7404
2 7408
7 74LS54
4 inverters to complement the inputs, 7 AOI for the segments, and 6 or
7 2-in AND to optimise and widen some of the AOI ANDs; utilisation of 9
& 1/6.
Based on the solutions and suggestions from the list, I drew up some
diagrams for the earlier problem:
http://www3.telus.net/~bhilpert/tmp/7seg.gif
A: 247,138 solution, suggested by several,
optimised down to 5 14/16-pin packages
B: 1-of-16 decoder with some optimisation, 5 packages (1 24-pin),
suggested by James and Vincent, IIRC
C: 247,253 data selectors solution suggested by Tony,
5 14/16-pin packages.
