PDP-8 on FPGA project & where is Hans Pufal?

Hi folks, I just found out that someone called Hans Pufal has already designes a PDP-8 on an FPGA device. I've been doing the same this year. My first approach ran on a Xilinx Spartan-3 (200K). It passed all basic tests and was able to run Chekmo. The system could be clocked with about 80MHz using Xilinx ISE's free XST compiler and mapping tools. After realizing that I would like to have a complete 8/e implementation (with more memory), I redesigned the whole thing a lot. The new design seemed more reasonable to me - but gets worse synthesis results. I still expect about 50-70 MHz in the end. The current version is not yet debugged. All memory is kept in FPGA onchip block rams. RAM is capsuled into a pdp8_memory module that can be altered in size (several versions exist) and adapted to different FPGA architectures. I have a kind of SoC-OMNIBUS which supports 2 to n cycle IO operations. Currently I only have a TTY implementation for it. The TTY seems to be 100% compatible to the original. RK8E or similar are planned. Cycle times: * Memory reference 2 * Operate 1 * Jump 1 * ISZ 3 Indirection, auto-index each add one cycle. My core will have a front panel interface that allows attachement of several flavors of front panel logic, including the original functionality and perhaps some more (I hate not being able to directly manipulate AC, for example!). I would like to know if there is any "public" interest in my project. I appreciate every help or ideas to merge my project into one of those nice front panel projects I've seen on the web. And now, please comment! Best wishes, Philipp :-) -- http://www.hachti.de