21 May
2013
21 May
'13
5:08 p.m.
On Tue, 21 May 2013, Chuck Guzis wrote:
On 05/21/2013 01:05 PM, Tony Duell wrote:
Interestingly, a 1 Mhz. 6502 in an Apple 2 can transfer 500Khz data rate
in programmed I/O mode. What it cannot do is take cycles to check the FDC
port status while in the transfer loop. There were all sorts of schemes
cooked up to work around this. I have an SVA "MegaFlex" controller that
had two almost identical software loops one page apart in memory. The
RDY* line on the FDC was used to toggle an address bit whenever it needed
to move between a "do nothing" loop and the "move data" loop. The do
nothing loop incremented the address in the other loop by in-line
modification (firmware ran in static RAM) and killed time until switched
over on the next sector. Clever, and worked well.
Another board from the same vintage used the WAIT line on the CPU to
handshake the transfer.
There were some DMA based controllers (Vista A800 comes to mind), but DMA
was always a bit iffy on Apple 2s.
Steve
--
The problem is that the higehr data rate on the
floppy drive leads to a
higher byte transfoer rate on the processor side of the disk controller.
Msot 8 bit machiens (certain of the Spectrom type) didn't use any form of
DMA fro the floppy controller, it relied o nthe processor to transfew the
bytes as neeeded. Doing this at the DD data rate normally involved some
tight code. I think doing it at the HD rate would be very hard/impossible/
A few years back, Herb Johnson opened a discussion of this on his web site.
The conclusion was that a 4 MHz Z80 was indeed fast enough to do this with
programmed I/O and DD 8" disks (500KHz data rate) and that it was *barely*
possible to do at 2 MHz Z80 set up correctly and not at all with a 2 MHz
8080.
I suggested a few schemes where the 8080 might be able to keep up, but they
were big (straight-line code) and used some odd techniques (e.g. PUSH instead
of STAX to do a 16-bit store and decrement). I never was curious enough to
try them--just hand-timed them.