18 Dec
2008
18 Dec
'08
11:03 p.m.
From: "Philipp Hachtmann"
Sent: Thursday, December 18, 2008 10:38 PM
You can emulate that in std_logic with a single driver driving an "H"
(the "pull-up"), and everyone else drives either "0" or
"Z".
As an ex-software guy, I find VHDL counter-intuitive and kinda ugly,
but it's what Hans used :-). I'm using the Xilinx ISE built in editor.
No, I'm trying to re-express everything in a few clock domains, namely
the timing pulses at the beginning of the cycle. The rest goes in the
combinatorial part of the thing:
if (tp4'event and tp4 = '1') then
fetch <= f_set;
defer <= d_set;
execute <= e_set;
word_count <= wc_set;
current_address <= word_count;
break <= b_set;
end if;
and dozens more like it :-).
The original
PDP-8's have these active low, and a logical OR is
implemented with wire-and, via open-collector drivers.
I know. But there's no
open collector logic in an FPGA (as I know). VHDL.
Nice. I like it, too :-)
Using Xemacs' VHDL mode. I'm hoping
to get around that by declaring TP1...TP4 (and *strobe*, etc.)
to be the clocks, and re-expressing the latches so that they are clocked
by an "official" clock. I don't know yet how well that is working out,
as it's buried in with the other 188 warnings-of-the-moment.
That still sounds **EVIL** !
FPGAs are made for fully synchronous designs with only a single clock (or
with a few clock domnains,
of course).
What you are doing is using LOTS of gated clocks. The tools don't like
that. They expect clocks
coming from global clock nets (GBUF for Xilinx). You have only a few of
these. I have another idea:
Write a D-flip-flop with R/S module and instantiate it in your design.
Make everything synchronous
to ONE system clock. DON'T use asynchronous stuff. FPGA can do real
latches, but everybody
(including the tools) start yelling if you do that....
Yeah, I've seen that.
Vince