14 May
2004
14 May
'04
5:40 p.m.
On 5/14/2004 12:01 PM -0500, cctech-request(a)classiccmp.org wrote:
Date: Fri, 14 May 2004 09:04:48 -0400
From: Brad Parker <brad(a)heeltoe.com>
Subject: Re: DEC RK07 drive interface specs wanted
Paul Koning wrote:
Another approach would be to wire the interface to address two different
registers; one for read, a different one for write. (use the R/W line to
select even/odd words) Still have latency issues, but less likely to show
bad bit combinations.
Dave.
.... Again, a software emulation may not get there
in time.
Yes, agreed. My plan was to be able to have the cpld "hold off" the
unibus cpu until the micro could "get there in time" in the cases where
that was needed. This is the heart of the shared-register-file-interlock
issue.
You might try to cheat by holding off SSYN on the
Unibus read until
any pending CSR fixups are done, but then the microcontroller has a
rather tight time limit (20 microseconds or so).
:-) as Homer Simpson says, "good idea, boss!"
My plan is to try and make that work. 20us is not a huge amount of time
but it is in the relm of the possible. Off the cuff I'd say it would be
tight for a 40mhz pic; it might be easier on an ARM7 with an fiq
interrupt. I plan to simulate the unibus hdl, figure out the window and
plan the micro and it's code around that window.
-brad