29 Apr
2013
29 Apr
'13
1:11 p.m.
On Apr 29, 2013, at 3:56 PM, Rob Doyle <radioengr at gmail.com> wrote:
On 4/29/2013 8:59 AM, David Riley wrote:
I think the 360/30 FPGA (http://www.ljw.me.uk/ibm360/vhdl/) does the
same. To be clear, it's DOABLE on an FPGA, but the timing analyzers
don't like it very much. Add to that the fact that the built-in
flip flops are strictly edge triggered in most technologies and you
have a hard time doing something as simple as an RS latch (some of
the true CPLDs around, like Xilinx's CoolRunner line, still have
true RS options available, but they're very small).
In general, if you're looking to implement something that was
originally designed around asynchronous logic in a modern FPGA,
you're generally better off trying to figure out how to make it run
with synchronous logic instead of implementing it 100% faithfully to
the schematic. A lot of the time, it's actually not particularly
hard to do; for example, microprocessor RD and WR lines often
implicitly act as clocks, which you can use to your advantage when
coding bus interfaces that use them.
- Dave
Clockless logic is something that comes up now
and then in ASIC
and FPGA circles, but it never seems to pan out (I remember Sun
doing something with it about a decade ago as well). I don't
know if it's because the tools are too hard to design or what,
but there must be some reason it never comes to anything (or at
least hasn't since the late '60s).
There is an IBM1130 CPU that is accurately implemented using
asynchronous logic in a standard FPGA.
See: http://ibm1130.blogspot.com/
This technique is probably not for the timid.