15 May
2014
15 May
'14
8:52 p.m.
On May 15, 2014, at 11:36 PM, Alan Hightower wrote:
Oh, then they've improved greatly since last I worked with them...
When Cypress was pushing them on our company, they were just a
bizarre proprietary core with an assembly of peripherals that
you could switch out. That was... 2008? Geez, that was 6 years
ago. So okay, maybe they've improved, and I forgot how long it's
been since I wrote them off.
I don't
think an FPGA is really necessary to maximize the speed (though a simple CPLD or one of
the really tiny FPGAs they're calling CPLDs these days might be a boon for sync mode).
However, I would love to work with the guy to bring it to a real microcontroller that has
a proper multi-bit SD controller and external bus interface, like one of the STM32 family,
instead of those dreadful PSoC chips. Maybe I'll drop him a line...
Huh? You apparently don't know what a PSoC is. It's a hybrid
programmable logic device and micro-controller. There are several
programmable logic blocks called UMBs inside the PSoC - each roughly
equivalent to a 22V10 SPLD. A PSoC has more macro cells than many CPLDs
and by far more data pump logic to/from the rest of the device. And the
micro-controller side is a "real microcontroller" - in fact the same
micro-controller core as your STM32 - an ARM Cortex M3. It does have a
proper multi-bit SDIO core, however it requires logic support from UMBs
and there may not be enough left over after the SCSI data pump. Yes, I agree a discrete CPLD/FPGA + STM32 would be
better performing
solution, however it would be more than twice the cost of a PSoC 5 in
just those ICs alone. I don't agree a standalone STM32 having to
bit-bang the SCSI side would perform better. Michael did a fabulous job.
I had started a design like it that evolved from a MachXO2+SiLabs M3
into a single PSoC 5, but Michael beat me to the finish line.
I don't think you'd have to bit-bang the SCSI if you had a CPLD
to do the transaction for you on the parallel bus. Does the
current rev of PSoC have a parallel bus with data ack? Seems
like that would probably solve the problem without significant
architectural changes.
Don't get me wrong, I think his design is pretty great. I just
figure that's where most of the bottleneck is coming in. And,
unlike everyone else (including me), he got it out the door
instead of optimizing it to death in his head. :-)
- Dave