1 Feb
2011
1 Feb
'11
1:54 p.m.
On 31/01/11 16:01, dwight elvey wrote:
What I mean by the error mask is that in the
polynomial, there is
a span of zeros. If you play it backwards until there are zeros in
all but the center portion where the zeros are, you have found
the error mask. Shifting it until is would be at the input edge of the
polynomial would give you the offset.
I noticed that Silicon Systems provided a different polynomial in the
SSI 32C452 datasheet:
x^32 + x^30 + x^26 + x^22 + x^15 + x^13 + x^6 + x^4 + x^0
0x14440A051
This polynomial is claimed to be capable of repairing up to an 8-bit
long error burst.
So what determines the longest error burst which can be corrected?
I hope this makes some sense?
Enough that I managed to figure out the algorithm -- with a little help
from:
* Adaptec AIC-100 Winchester Controller Chip datasheet -- VERY nice
description of the 5-bit error correction algorithm, but no polynomials.
* SSI 32C452 datasheet -- reasonable description of how
error-correction works
* NatSemi AN-413 -- good description of most disk-related subjects,
but out-and-out wrong in places. Do your own math, and find a secondary
reference for anything you find in here!
* WD 1002-05 Winchester controller OEM manual -- polynomials are
listed on page 1-3
* WD 1014 Error Detection/Support Logic Device datasheet -- p. 4-19
explains what parts of the disc data are included in the CRC calculation.
Note that the binary polynomial is loaded into the SSI chip shifted one
bit to the right and ANDed by 0x7FFFFFFF. To get the real polynomial as
you'd use for the XOR factor in a CRC32 routine, shift it one bit left
and set the LSbit (OR with 0x01).
Also note that AN413 has an incorrect binary value for the polynomial:
x^32 + x^28 + x^26 + x^19 + x^17 + x^10 + x^6 + x^2 + x^0
is really 0x1140A0445, not 0x140A0443. This cost me quite a few hours of
debugging...
And yes, the A1F8 header block is included in the CRC... the IV is
0xFFFFFFFF, then the first bytes clocked in are A1 followed by F8. Data
bits are clocked into the LFSR in order MSB to LSB. The CRC is stored on
the track as a 4-byte big-endian value. Clock everything from A1 to the
last CRC byte in exactly as it is, and you'll get a CRC remainder of
zero if the track data is valid. If it's anything else, do a couple of
re-reads (three or four), and if all else fails... bail out and do the ECC.
That was a "fun" way to spend two days... Ah well, long code-fests
aren't all bad when you've got some nice music and a big pot of tea on
standby. Snow Patrol, the Dixie Chicks, Genesis, Little Big Town, Sting
and The Police....
--
Phil.
classiccmp at philpem.me.uk
http://www.philpem.me.uk/