On Thu, Jan 02, 2014 at 04:40:46PM -0500, Paul Koning wrote:
On Jan 2, 2014, at 11:15 AM, Peter Corlett <abuse
at cabal.org.uk> wrote:
[...]
Verilog claims
to be C-like, but this isn't particularly true. Some of its
expression syntax is C-inspired, but you could describe it as Perl-like or
Java-like at that point! It's somewhat more Perl-like in that you can just
glue fragments together and it'll generally work. Even a rank amateur like
myself managed to get a blinking LED after barely twenty hours or so of
effort :)
I don?t know Verilog, but if it really is PERL-like that?s quite a
strong
condemnation.
Oi, I've been a professional Perl software developer for the last fifteen
years, and it's not that bad a language :p
However, I do know the kind of Perl you've seen, which has been slapped
together by non-programmers who just want to glue together a few CPAN modules
to get the job done. Many of the major CPAN modules have been written by
professional programmers, come with good test coverage and documentation, and
are high-quality reusable components.
CPAN modules are analogous to IP cores, and likewise, if one just wants to
bodge together a few cores for a project without taking a course in chip
design, Verilog seems to be a pretty handy tool for that task.
[...]
VHDL is clearly inspired by Ada. I?ve done some
elementary VHDL work and like
it a lot. FWIW, there is an open source VHDL simulator available (just a
simulator, not tied to any real world FPGA) that?s integrated into GCC ?
called GHDL. It seems to work well; I?ve fed it some rather large models that
simulate nicely.
OK, now *that* is enough to lure me into the VHDL world. I stumbled with my
Verilog experiment when I'd created a design and couldn't figure out how to
verify the damn thing worked. Being able to do a quick "make -j8 test" on a
proper computer definitely beats having to fire up Windows and then swear at
the sluggish and inscrutable Quartus II.
(GHDL will even ships with the upcoming Debian "jessie"!)