13 May
2001
13 May
'01
3:23 p.m.
From: Tony Duell <ard(a)p850ug1.demon.co.uk>
care.
Yes, that is a spec'ed item delay after index. The cheap fix, delay
index
about 95% of one revolution, fakes it into thinking it occured earlier.
> some don't, but I can't remember which
FDCs do/don't (I think WD 37C65
etc
need it but
NatSemi DP8473 and WD 1770/1772 don't care).
I seem to remember a problem something like : 765s and related
controllers (by practical experimentm, the 37C65 is one of these) will
miss a sector header (and thus be unable to read the sector) if it comes
too soon after the index pulse. The WD177x and 179x, etc don't seem to The 765 and the 8272 are essentially the same chip.
They use an external
No the ARE the same chip, at one point NEC made them for Intel.
data separator circuit, and in most PC disk controllers
this is
configured for DD operation only. If there's the well-known 9216 8 pin
data
separator chip, you might be able to get that to run in
single-density
mode (Inverting the MFM select output of the 8272 and feeding it to pin
5
(cut the track that grounds this pin of course) of the
9216 often works
for _reading_. Writing involves modifying the write precompensation
circuit.
Depends on the precomp needed. for single density it's fairly lax, for DD
that might require tweeking or not.
If the data separator is several smaller chips (like
the original IBM
FDC
card), it's a lot more work.
If you have the drawings, it may be easier. Many more parameters are
alterable that way.
I think the 37C65 should work in single density mode,
but it's a long
time since I read the datasheet.
It will do single and double 8", unless the board compromized and
used a half speed clock.
And my experience of other disk controller chips (UMC,
etc) is that
while
they may be documented as working in SD mode, they
don't. At least not
reliably.
It's a setup and config issue.
Allison