14 Jan
2014
14 Jan
'14
4:52 p.m.
On Jan 14, 2014, at 9:46 AM, Mouse <mouse at rodents-montreal.org> wrote:
My recollection is that it's an artifact of some space-saving
tricks used in NMOS processes that precharge some gates on one
half of the clock cycle instead of using flip-flops. It
essentially makes some temporary registers out of DRAM, which
means you can't hold it indefinitely. You could, theoretically,
do the same thing in CMOS. My other recollection (which is
somewhat less sure) is that you can hold the 'EC000 static on
one half of the clock, whereas the 'SEC000 allows both.
- Dave
The SEC is
essentially the EC with a core that can be run static
(i.e. you can stop the clock with no ill effect).
I've wished more CPUs were like that, ie, had no minimum clock
frequency. It makes some kinds of hacking-around easier. (I've never
really understood why any CPU would have a minimum clock frequency,
short of things like on-die clock multipliers.)