Disc analyser news update

Sure.. But there are several problems with that approach. The main one is that a breakpoint is intrusive, it changes the behaviour of the system. You can't sensibly put a breakpoint in a time-critical routine. But you certainly can monitor the program flow in such a routine with a logic analyser, assuming you can get access to the program store address bus. And a logic analyser will tell you different things to a breakpoint. OK, at a breakpoint (if the debugging hardware is designed sensibly), you can exame CPU registers, etc. But it woun't necessarily tell you how the code got to the breakpoint. A logic analyser will/ Another problem is that you are depending on the microcontoller chip to be mostly working properly for the JTAG port to work. Which is likely, but not certain, to be the case. And of course for me there's the prcatical problem of not having a JTAG interface. Yes, I know it's just a few TTL lines clocking data in and out serially. It's not hard to bit-bang, but it's one more thing to debug. And if I make a mistage in the JTAG hardware, or more likely in the code to drive it, I am going to be going round in circles looking for the problem. I am not taliking about FPGAs... I'd rather not design with them, thank you. And it is IMHO falacious to assume that because something is a good method in once case, it has to be the right method in all cases. -tony