10 Jun
2007
10 Jun
'07
12:03 a.m.
On 10 Jun 2007 at 0:06, Peter wrote:
I was thinking about the Z0765A FDC and how to make it
compatible with a
300rpm FDD. It seems that all that needs to be done (in theory) is to
reduce all the FDC clocks by half - the 8MHz clock to 4MHz and the Write
Clock to 500KHz. (NEC indicates this in their uPD 765A datasheet). Clearly
not as simple to execute as it sounds, but not beyond the realms of
possibility.
Actually, you don't need to change CLK (on pin 19), just WCLK on pin
21--on the 765, CLK is pretty much independent of the data rate. So
you can leave it at 8 MHz.
I haven't looked at the schematic, but you may also need to either
synthesize a "drive ready" signal or use a 720K drive that has the
capability of providing one, say, a Teac FD235F.
Hope this helps.
Cheers,
Chuck