1 Oct
2010
1 Oct
'10
7:01 p.m.
Chuck Guzis wrote:
I can't seem to derive a stable expression
(Verilog) for adding two
numbers, A and B,in ones' complement without computing A+B and A+B+1
as a two's complement adder and then selecting one or the other
result depending on the carry-out. This seems to me to be a huge
waste of logic.
Has anyone in their FPGA simulations ever run into this one and come
up with a clever solution?
Umm... the use of two adders and a mux *IS* the clever
solution. Unless
you're going to have a large array of one's complement adders for some
reason, the resource utilization will be in the noise. It is also
generally faster than most (if not all) other ways of implementing one's
complement addition.
Unfortunately Sun managed to patent this in 1999, despite it having been
common practice for many years. US patent number 6,343,306. I haven't
tried to find specific prior art, but I recall seeing it done that way
in the early 1980s.
The other clever way to do it, if you happen to have a two's complement
adder that has a Generate output for carry lookahead (which you won't
have in an FPGA, unless you implement it yourself), is to tie the
Generate output to the carry input. Honeywell had a patent on that, now
expired: US 4,298,952.
Eric