26 Sep
2005
26 Sep
'05
2:18 p.m.
der Mouse wrote:
Just that all of them gets refeshed in the alloted time.
Note they just have to be read for refesh. Still you better
check the data sheets if you got them for the fine print.
When connecting
DRAM chips to the pins of a SIMM (i.e. laying out the
traces) does it matter if the order of the address and data lines is
preserved? [...]
What about refreshes? (This is a question, not a challenge; I do not
know enough about how dynamic RAM refresh works to know whether this
really is relevant. But it seems to me that it might be.)